1. Field of the Invention
The present invention relates to a semiconductor device having an alignment mark or an overlay mark for an overlay accuracy inspection using a vapor phase HF treatment process in a manufacturing process of a cylindrical storage node thereof, and a method of producing the semiconductor device.
2. Discussion of Background
In a semiconductor device such as a DRAM in which large-scale integration is required, microminiaturization of a memory cell is an indispensable technique and it is necessary to maintain capacitance of capacitors besides the microminiaturization of the elements. Accordingly, a method of increasing an area of stack electrodes by adopting a three-dimensional structure like a cylinder, a fin or a tunnel for the shape of stack electrodes was examined. A DRAM having a cylindrical capacitor is described in the below.
FIG. 9 is a cross-sectional view of the cylindrical capacitor constituting a DRAM memory cell formed by a conventional method of producing semiconductor device disclosed in Japanese Unexamined Patent Publication No. Hei 6-196649 (JP-A-6-196649).
In FIG. 9, numeral 101 designates a semiconductor substrate; numeral 102 designates a boro-phosho silicate glass(BPSG) film laminated on a surface of the semiconductor substrate 101; numeral 103 designates a silicon oxide film laminated on a surface of the BPSG film 102 by a CVD method, through the BPSG film 102 and the silicon oxide film 103 a storage node contact 104 made of a conductive film is formed so as to be in contact with an impurity region formed on a surface region of the semiconductor substrate 101. Further, a storage node 105 in a cylindrical shape which extends in the vertical direction and be in contact with an upper portion of the storage node contact 104 while hanging over an upper surface of the silicon oxide film 103 is formed. Further, on a surface of the storage node 105, an upper electrode 107 is laminated interposing a dielectric film 106, wherein a cylindrical capacitor 108 is fabricated by the storage node 105, the dielectric film 106 and the upper electrode 107.
In a case that the semiconductor device shown in FIG. 9 was formed, after the storage node contact 104 was formed, a conductive material constituting a bottom portion of the storage node 105 was patterned. When a mask pattern necessary for the patterning is formed by a photomechanical process, it is indispensable to align the surface of the semiconductor substrate 101 using an alignment mark thereon. Also, in order to obtain the semiconductor device having a good formation, it is indispensable to form an overlay mark in the semiconductor substrate 101 and to inspect an overlay accuracy thereby.
In the next, the method of producing the cylindrical capacitor shown in FIG. 9 is described in reference of FIGS. 10a through 10f. Further, a method of forming the alignment mark which is formed simultaneously is described in reference of these figures as a conventional technique. In FIGS. 10a through 10f, the left halves show a memory cell region having a cylindrical capacitor; and the right halves show a mark region having a mark opening portion which will be an alignment mark or an overlay mark.
As shown in FIG. 10a, on the surface of semiconductor substrate 101, the BPSG film 102 and the silicon oxide film 103 are successively laminated, and a resist pattern 109 having openings corresponding to a storage node contact hole 110 and a mark opening portion 111 is formed thereon. Further, the silicon oxide film 103 and the BPSG film 102 are subjected to an anisotropic etching using the resist pattern 109 as etching mask to thereby make the storage node contact hole 110 and the mark opening portion 111.
The opening diameter of storage node contact hole 110 is about 0.3 .mu.m; the opening diameter of mark opening portion 111 is about 4 .mu.m; and the plan view of the opening portions is in a rectangular shape.
In the next, as shown in FIG. 10b, the resist pattern 109 is removed and a phosphorus doped polysilicon 112 is laminated on the surface of silicon oxide film 103 so as to fill the inside of storage node contact hole 110, whereby a storage node contact 104 is obtainable. At this time, the phosphorus doped polysilicon 112 is similarly laminated in the inner wall of mark opening 111 simultaneously. The surface shape of phosphorus doped polysilicon laminated in the mark opening portion 111 becomes concave in accordance with the shape of mark opening portion 111.
Further, a BPSG film 113 is laminated to obtain a film thickness corresponding to the vertical dimension of the cylindrical capacitor. A resist pattern 114a having a shape corresponding to a bottom portion of the storage node 105 and a resist pattern 114b having a shape covering the mark opening portion 111 are formed above the phosphorus doped polysilicon 112.
Thereafter, as shown in FIG. 10c, the BPSG film 113 and the phosphorus doped polysilicon 112 are continuously subject to a dry etching using the resist pattern 114a and the resist pattern 114b as etching mask to obtain the patterned phosphorus doped polysilicon 112a, the patterned BPSG film 113a, the patterned phosphorus doped polysilicon 112b and the patterned BPSG film 113b, respectively having shapes corresponding to the etching masks.
In the next, as shown in FIG. 10d, a phosphorus doped polysilicon 115 is laminated until it has a predetermined film thickness; and further the phosphorus doped polysilicon 115 is subject to an anisotropic etching as shown in FIG. 10e to thereby obtain a sidewall 115a made of a conductive material in the sidewalls of BPSG film 113a and the side of phosphorus doped polysilicon 112a. At the same time, in the mark region, a sidewall 115b deposited on the side of the BPSG film 113b and the side of the phosphorus doped polysilicon 112b are formed and a sidewall 116 are formed on a surface of BPSG film 113b.
Thus the cylindrical storage node 105 is fabricated by the sidewall 115a and the phosphorus doped polysilicon 112a, and the mark 117 is fabricated by the sidewall 115b and the phosphorus doped polysilicon 112b.
In the next, as shown in FIG. 10f, the BPSG film 113 is removed by a vapor phase HF treatment process.
By forming the dielectric film 106 and the upper electrode 107 respectively, it is possible to make the cylindrical capacitor 108.
However, as mentioned in the above, when the mark 117 was formed in the process of forming the cylindrical capacitor 108, the sidewall 116 formed in the mark region in the prior step was lifted off at the time of vapor phase HF treatment process as shown in FIG. 10f. Accordingly, there was a problem that a plurality of elements which should have been electrically insulated were shorted when the lifted-off sidewall 116 was deposited again on the memory cell because the sidewall was made of the conductive material, wherein yield was dropped.
Also there was a problem of a drop of yield caused by the lift-off of the conductive material like sidewall in forming the overlay mark.
Another technique of forming an alignment mark is disclosed in Japanese Unexamined Patent Publication No. Hei 7-142379 (JP-A-7-142379).
This technique is to solve inconvenience that a circuit pattern is shorted by a deposition of a peeled-off aluminum alloy in an active element region by preventing the aluminum alloy from remaining in an inner wall of opening as sidewall in a later step of forming wiring when the area of opening of an alignment mark is as much as 4 .mu.m.times.4 .mu.m or 4 .mu.m.times.2 .mu.m.
According to this technique, the shape of opening of the alignment mark is formed by assembling a plurality of micro openings; the size of one side of the micro openings is 1 .mu.m or less; the opening portion is completely filled in at a stage of laminating the wiring of aluminum alloy; and the sidewall made of the conductive film is not formed in an alignment mark region when the wiring is patterned.